1. Field of the Invention
This invention relates to an implementation of a digital signal processor (DSP) architecture for use as a digital interpolation filter or a digital decimation filter.
2. Discussion of Related Technology
Commonly utilized DSP architecture for digital interpolation or digital decimation filters employ bit multiplication schemes that require hardware to perform a series of shifts and adds to multiply data by a particular filter coefficient. This typically requires the use of an adder for each group of bits to be multiplied where the number of adders is greater than one half the number of bits of the filter coefficient to be multiplied.
These commonly utilized filter also typically do not include a common data path for multiplication scaling of the numbers to be multiplied and accumulation of the products.